1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory device which can electrically write only once, especially a semiconductor nonvolatile memory device which performs writing of a program by breaking down a transistor, and a method of writing thereto.
2. Description of the Related Art
Generally, in a semiconductor integrated circuit, compensation or adjustment accompanied by dispersion compensation of a threshold voltage or change of operational condition of a transistor is required to improve the yield rate and stabilize the quality.
In an electronic timepiece (watch or clock), by oscillating a crystal resonator in an oscillation circuit provided in a complex circuit for the timepiece, a clock signal which is a standard of measuring time is generated. When a tuning-fork-type crystal resonator is used, some dispersion is created in the frequency of the clock signal due to a slight difference in size caused by the processing accuracy.
Thus, adjustment of a digital frequency by means of the circuit to raise an accuracy of a slightly dispersed clock signal generated from the oscillation circuit using the crystal resonator having an accuracy of one second level of a timepiece to an accuracy of ppm (part per million) is referred as DF adjustment.
The DF adjustment of the conventional timepiece will be explained with reference to FIG. 7 to FIG. 10.
A principle of the DF adjustment will be explained with circuit diagrams in FIG. 7 and FIG. 8, and a time chart in FIG. 9.
FIG. 7 is a block circuit diagram showing a structure of a conventional DF adjustment circuit. The circuit is defined by an oscillation circuit 23 using a crystal resonator 18, a dividing circuit 24, a DF adjustment timing circuit 25, a DF adjustment data reading circuit 26, a plurality of DF adjustment terminals 27, and a plurality of AND circuits 28.
The dividing circuit 24 is composed by a plurality of flip-flop circuits 29a to 29e (hereinafter, abbreviated to FF circuit).
In the drawing, the solid arrow line indicates the DF adjustment data reading signal Sa, a broken arrow line indicates a DF adjustment data signal Sb, and a dashed arrow line shows an input and output direction to each circuit of the DF adjustment timing signal Sc, respectively.
FIG. 8 shows a concrete example of the circuit diagram of the DF adjustment data reading circuit 26 in FIG. 7. The DF adjustment data reading circuit 26 is composed by a plural number of invertors 33 and NOR circuits 34 in the same number thereof.
The electric source voltage V.sub.DD is inputted to each invertor 33 through each DF adjustment terminal 27 respectively, the reversal output by each invertor 33 is inputted to an input terminal on one side of each NOR circuit 34, the DF adjustment data reading signal Sa is inputted by commonly connecting the other input terminals of each NOR circuit 34, and the output terminal of each NOR circuit 34 is connected to an input side of each invertor 33. The output signal of each NOR circuit 34 is a DF adjustment data signal Sb.
FIG. 9 is a time chart of an output signal from the first FF circuit 29a to the fifth FF circuit 29e which constitute the dividing circuit 24 in relation to the DF adjustment data reading signal Sa and the DF adjustment timing signal Sc shown in FIG. 7.
In FIG. 9, T1 indicates the timing when the DF adjustment data reading signal Sa changed to a high level "H", and T2 indicates the timing when the DF adjustment data reading signal Sa changed to a low level "L", respectively. In addition, T3 indicates the timing when the DF adjustment timing signal Sc is set to a high level "H".
In FIG. 7, an output signal of the oscillation circuit 23 is inputted to the first FF circuit 29a constituting part of the dividing circuit 24, and operation of the dividing circuit 24 starts.
At the timing T1 in FIG. 9, the DF adjustment timing circuit 25 receives the output signal of the dividing circuit 24, and outputs the DF adjustment data reading signal Sa which is usually in a level of "L", for several milliseconds in a level of "H".
When the DF adjustment data reading signal Sa is "H", all output signals of all NOR circuits 34, which constitute the DF adjustment data reading circuit 26 shown in FIG. 8, become "L".
At this time, when the signal from each DF adjustment terminal 27 is in a level of "H" corresponding to the electric source voltage V.sub.DD, pulling of electric potentials against each other occurs between the output of each NOR circuit 34 and each DF adjustment terminal 27, and the input signal of each invertor 33 and the output signal of each NOR circuit 34 is changed to a level of "H", while the output signal of each invertor 33 changed to a level of "L".
When the DF adjustment data reading signal Sa becomes "L" at the timing T2 in FIG. 9, since two input signals of each NOR circuit 34 in FIG. 8 as well as the output signal of the invertor 33 becomes "L", the output signal of each NOR circuit 34 becomes "H".
However, if any one of plural DF adjustment terminals 27 is selectively cut, the pulling of electric potentials against each other does not occur between the output signal of the NOR circuit 34 which connects with the above described cut DF adjustment terminal 27, and the DF adjustment terminal 27. Accordingly, while the DF adjustment data reading signal Sa is in a "H" state, the output signal of the NOR circuit 34 is "L" and the output of the invertor 33 is "H".
Even when the output of the DF adjustment data reading signal Sa becomes "L" at the timing T2 in FIG. 9, since the input signals into the NOR circuit 34 are "L" and "H", the output signal of the NOR circuit 34 remains in a "L" state.
In other words, when the output signal of the NOR circuit 34 is required to remain in a "L" state, it can be realized by only cutting the DF adjustment terminal 27 corresponding to the NOR circuit 34 needed.
The output signal of each NOR circuit 34 in the DF adjustment data reading circuit 26 becomes a DF adjustment data Sb, which is inputted to each AND circuit 28 shown in FIG. 7.
The DF adjustment timing circuit 25 in which the DF adjustment data reading signal Sa is again changed to "L" from "H" at the timing T2 shown in FIG. 9 makes the DF adjustment timing signal Sc, which is usually in a "L" state, be in a "H" state only in a moment at the timing of T3 shown in FIG. 9, thereby the output signal of the AND circuit 28 becomes "H" only in a moment when the DF adjustment timing signal Sc becomes "H", if the DF adjustment data Sb is "H".
At this time, all output signals of the FF circuits 29a to 29e constituting the dividing circuit 24 are in a "L" state, only a FF circuit 29 corresponding to the AND circuit 28 in which the output signal is in a "H" state has an output signal in a "H" state, and the dividing circuit 24 moves a little faster than the actual. Thus, it is possible to perform the digital frequency adjustment of the clock signal through the circuits.
Next, writing of the DF adjustment data will be explained with reference to FIG. 10. FIG. 10 is a schematic plane view showing a conventional complex circuit for a timepiece.
The complex circuit of a timepiece consists of a DF adjustment terminal 27, IC 36, and a crystal resonator 18 provided on a complex circuit substrate 35. In FIG. 10, a white circle portion 38 indicates a hole opened so as to cut the DF adjustment terminal 27 by a cutting means such as a drill.
Judgement of the DF adjustment data is determined by checking whether any one of a data signal connecting to the DF adjustment terminal 27 and a data signal without connecting to the DF adjustment terminal 27 is inputted or not, that is, whether from any one of plural DF adjustment terminals 27 the signal by the electric source voltage V.sub.DD is inputted to the IC 36 or not.
Consequently, by cutting the DF adjustment terminal 27 shown in FIG. 10 with a cutting means such as a drill, the corresponding DF adjustment data Sb is changed to a "L" state, while by not cutting the DF adjustment terminal 27, the corresponding DF adjustment data Sb has a "H" state.
Thus, in the complex circuit for a timepiece (watch and clock) shown in FIG. 10, the DF adjustment is performed by setting the DF adjustment terminals 27 by the same number of the DF adjustment data, and by cutting only a DF adjustment terminal 27 to which a program is to be written in, with a mechanical cutting means such as a drill.
In order to carry out the writing of a program through this method, input/output terminals for this purpose are required to be provided on the IC 36 in the same number as the DF adjustment terminals 27.
Since the input/output terminal has an area of 100 .mu.m.sup.2 per piece, if the same number of input/output terminals and DF adjustment terminals are provided on the IC 36, the area of the IC 36 needs to be very large.
When the area of the IC 36 gets large, the ratio of the area occupied by the IC on the complex circuit board 35 becomes high, and at the same time the area efficiency in relation to wafer area decreases and number of IC tips obtainable from a sheet of wafer becomes small.
Furthermore, since the writing of a program is performed by a mechanical cutting means such as a drill, it takes a long period of time for the processing.